`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:37:41 05/31/2007 
// Design Name: 
// Module Name:    divider_fsm 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module divider_fsm(START, GE, LAST, Q, LR, RR, SR, SQ, FIRST, READY, D);
	input START;
	input GE;
	input LAST;
	input [3:0] Q;
	
	output LR;
	output RR;
	output SR;
	output SQ;
	output FIRST;
	output READY;
	output [3:0] D;

	wire P_IDLE, P_SETUP, P_TEST, P_SUB;
	wire N_IDLE, N_SETUP, N_TEST, N_SUB;

	assign P_IDLE	=	Q[3];
	assign P_SETUP	=	Q[2];
	assign P_TEST	=	Q[1];
	assign P_SUB	=	Q[0];
	
	assign D[3]	= N_IDLE;
	assign D[2] = N_SETUP;
	assign D[1] = N_TEST;
	assign D[0] = N_SUB;
	
	assign N_IDLE	=	(~START & P_IDLE) |
							(LAST & P_TEST);
							
	assign N_SETUP	=	(START & P_IDLE);
	
	assign N_TEST	=	(P_SETUP) |
							(P_SUB) |
							(~GE & ~LAST & P_TEST);
							
	assign N_SUB	=	(GE & ~LAST & P_TEST);
	
	assign LR		=	(GE & ~LAST & P_TEST);
	
	assign RR		=	(START & P_IDLE);
	
	assign SR		=	(P_SETUP) |
							(~GE & ~LAST & P_TEST) |
							(P_SUB);
	
	assign SQ		=	(P_SETUP) |
							(~LAST & P_TEST);
							
	assign FIRST	=	(P_SETUP);
	
	assign READY	=	(P_IDLE);
endmodule