`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    05:34:26 05/31/2007 
// Design Name: 
// Module Name:    fsm_game 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fsm_game(go, timer, tc8s, enter, tc8a, lsfr, ldon, treset, ldreg, ldresp, start, sr, ar, Q, D);
	input go;
	input timer;
	input tc8s;
	input enter;
	input tc8a;
	input [3:0] Q;
	
	output lsfr;
	output ldon;
	output treset;
	output ldreg;
	output ldresp;
	output start;
	output sr;
	output ar;
	output [3:0] D;
	
	wire P_IDLE, P_SHOW, P_ASK, P_CHECK;
	wire N_IDLE, N_SHOW, N_ASK, N_CHECK;
	
	assign P_IDLE	=	Q[3];
	assign P_SHOW	=	Q[2];
	assign P_ASK	=	Q[1];
	assign P_CHECK	=	Q[0];

	assign D[3] = N_IDLE;
	assign D[2]	= N_SHOW;
	assign D[1] = N_ASK;
	assign D[0] = N_CHECK;
	
	assign N_IDLE	=	(~go & P_IDLE) |
							(tc8a & P_CHECK);
	
	assign N_SHOW	=	(~tc8s & P_SHOW) |
							(go & P_IDLE);
	
	assign N_ASK	=	(~enter & P_ASK) |
							(tc8s & P_SHOW) |
							(timer & P_CHECK & ~tc8a);
	
	assign N_CHECK	=	(~timer & ~tc8a & P_CHECK) |
							(enter & P_ASK);
	
	assign lsfr		=	(~go & P_IDLE);
	assign ldon		=	(~go & P_IDLE);
	assign treset	=	(go & P_IDLE) |
							(tc8s & P_SHOW) |
							(enter & P_ASK);
	assign ldreg	=	(enter & P_ASK);
	assign ldresp	=	(~timer & P_CHECK);
	assign start	=	(tc8a & P_CHECK);
	assign sr		=	(go & P_IDLE);
	assign ar		=	(tc8s & P_SHOW);
endmodule