`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    11:11:57 05/01/2007 
// Design Name: 
// Module Name:    hex7seg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module hex7seg(co, s2, s1, s0, ca, cb, cc, cd, ce, cf, cg);
    input co;
    input s2;
    input s1;
    input s0;
    output ca;
    output cb;
    output cc;
    output cd;
    output ce;
    output cf;
    output cg;

    wire ca0;
	 wire ca1;
	 wire ca2;
	 wire ca3;
	 
	 and(ca0, ~co, ~s2, ~s1, s0);
	 and(ca1, ~co, s2, ~s1, ~s0);
	 and(ca2, co, ~s2, s1, s0);
	 and(ca3, co, s2, ~s1, s0);
	 or(ca, ca0, ca1, ca2, ca3);
	 
	 wire cb0;
	 wire cb1;
	 wire cb2;
	 wire cb3;
	 wire cb4;
	 wire cb5;
	 
	 and(cb0, ~co, s2, ~s1, s0);
	 and(cb1, ~co, s2, s1, ~s0);
	 and(cb2, co, ~s2, s1, s0);
	 and(cb3, co, s2, ~s1, ~s0);
	 and(cb4, co, s2, s1, ~s0);
	 and(cb5, co, s2, s1, s0);
	 or(cb, cb0, cb1, cb2, cb3, cb4, cb5);
	 
	 wire cc0;
	 wire cc1;
	 wire cc2;
	 wire cc3;
	 
	 and(cc0, ~co, ~s2, s1, ~s0);
	 and(cc1, co, s2, ~s1, ~s0);
	 and(cc2, co, s2, s1, ~s0);
	 and(cc3, co, s2, s1, s0);
	 or(cc, cc0, cc1, cc2, cc3);
	 
	 wire cd0;
	 wire cd1;
	 wire cd2;
	 wire cd3;
	 wire cd4;
	 wire cd5;
	 
	 and(cd0, ~co, ~s2, ~s1, s0);
	 and(cd1, ~co, s2, ~s1, ~s0);
	 and(cd2, ~co, s2, s1, s0);
	 and(cd3, co, ~s2, ~s1, s0);
	 and(cd4, co, ~s2, s1, ~s0);
	 and(cd5, co, s2, s1, s0);
	 or(cd, cd0, cd1, cd2, cd3, cd4, cd5);
	 
	 wire ce0;
	 wire ce1;
	 wire ce2;
	 wire ce3;
	 wire ce4;
	 wire ce5;
	 
	 and(ce0, ~co, ~s2, ~s1, s0);
	 and(ce1, ~co, ~s2, s1, s0);
	 and(ce2, ~co, s2, ~s1, ~s0);
	 and(ce3, ~co, s2, ~s1, s0);
	 and(ce4, ~co, s2, s1, s0);
	 and(ce5, co, ~s2, ~s1, s0);
	 or(ce, ce0, ce1, ce2, ce3, ce4, ce5);
	 
	 wire cf0;
	 wire cf1;
	 wire cf2;
	 wire cf3;
	 wire cf4;
	 
	 and(cf0, ~co, ~s2, ~s1, s0);
	 and(cf1, ~co, ~s2, s1, ~s0);
	 and(cf2, ~co, ~s2, s1, s0);
	 and(cf3, ~co, s2, s1, s0);
	 and(cf4, co, s2, ~s1, s0);
	 or(cf, cf0, cf1, cf2, cf3, cf4);
	 
	 wire cg0;
	 wire cg1;
	 wire cg2;
	 wire cg3;
	 
	 and(cg0, ~co, ~s2, ~s1, ~s0);
	 and(cg1, ~co, ~s2, ~s1, s0);
	 and(cg2, ~co, s2, s1, s0);
	 and(cg3, co, s2, ~s1, ~s0);
	 or(cg, cg0, cg1, cg2, cg3);
endmodule